1. Field of the Invention
The present invention is related to a data handover unit for transferring data between different clock domains, particularly between clock domains having different clock frequencies. The present invention is further related to a method for operating a data handover unit.
2. Description of the Related Art
In high-speed data devices, incoming high-speed data have to be securely handed over from a high-speed receiver to a protocol layer of a high-speed serial link. Usually, the clock domain of the incoming high-speed data and the clock domain of the protocol layer are different in frequency/data rate, in a worst case by a non-even or a non-integer multiplication factor. In a standard approach, a high-speed FIFO is used to safely carry out the transition from the first clock domain to the second clock domain. Therein, the high-speed FIFO has to synchronize the two different clock domains and therefore includes a plurality of flip-flops which are operated at the high clock frequency of the first clock domain which will cause an issue due to the increase in power consumption. In addition, the high-speed FIFO will add latency to the receive path which would be a critical issue, e.g., for a DRAM product. Furthermore, the FIFO would have to operate at two different frequencies at the boundary between the two internal clock domains, thus requiring costly internal clock and clock-phase generation circuits.
In another approach, the serial high-speed data is latched in a pointer from which the data bits of a data frame is transferred to a barrel shifter which is clocked by the second lower frequency clock of the second clock domain. Therein, the transferring of the data frame bits to the barrel shifter is critical in timing as the setup and hold times of the pointer and the first high-speed clock domain has to be met.